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Transient and Permanent Error Control for Networks-on-Chip by Qiaoyan Yu

By Qiaoyan Yu

This e-book addresses reliability and effort potency of on-chip networks utilizing cooperative blunders keep an eye on. It describes a good method to build an adaptive blunders keep watch over codec in a position to monitoring noise stipulations and adjusting the mistake correction energy at runtime. tools also are offered to take on joint brief and everlasting errors correction, exploiting the redundant assets already to be had on-chip. A parallel and versatile community simulator is usually brought, which enables interpreting the influence of assorted mistakes keep an eye on equipment on network-on-chip performance.

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16) 28 2 Existing Transient and Permanent Error Management in NoCs 2 1 6 61 6 H¼6 6 .. 6. 4 1 ab abþ1 .. abþ2td À1 3 À b Á2 À b ÁnÀ1 a ÁÁÁ a À bþ1 Á2 À bþ1 ÁnÀ1 7 7 a ÁÁÁ a 7 7 7 .. .. 7 . . 17) in which, ab, . , ab+2tdÀ1 are roots of the generator polynomial g(x). 17). Each element in the equation is represented with an m-bit vector. 18). 19), which can be solved by PetersonGorenstein-Zieler algorithm, Euclid’s algorithm, Berlekamp-Massey algorithm (BMA) [15] and inversionless BMA [26]. 19) j¼1 The obtained s(x) is one row polynomial of the H matrix.

In this chapter, we will review the state-of-the-art techniques for transient and permanent error management in NoCs. 1 Error Control Schemes Three typical error control schemes are used in on-chip communication: error detection combined with automatic repeat request (ARQ), hybrid ARQ (HARQ) and forward error correction (FEC). The generic diagram for transmitter and receiver is shown in Fig. 1. ARQ and HARQ use not acknowledge (NACK) signal to request transmitter resending message. FEC does not need acknowledgement signal to recover detected error; instead, it corrects error immediately if error is identified in receiver.

In Proc Intl SoC Design Conf I-129–I-133 36. Bobda C et al (2005) DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices. in Proc Intl Conf on Field Programmable Logic and Applications. 153–158 37. Zhang Z, Greiner A, Taktak S (2008) A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip. in Proc IEEE Design Automation Conf (DAC’08) 441–446 38. Koibuchi M, Matsutani H, Amano H, Pinkston TM (2008) A lightweight fault-tolerant mechanism for network-on-chip.

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