By Ronald F. Ayres
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Extra resources for VLSI: Silicon Compilation and the Art of Automatic Microchip Design
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The expression + 1 FOR I FROM 1 TO 15; represents the sum of 1 as I runs from I to 15, or more simply, this expression counts the number of iterations caused by the quantifier. Similarly, if LIST is of type NOR-COLUMN-LOGIC, a list of boolean values, and if B is of type BOOLEAN, then + 1 FOR B $E LIST;- represents the length of LIST; that is, it sums up Is, one 1 per iteration. We can define our new NOR-UNIT function, which NOR-COLUMN-LOGIC, by writing: DEFINE takes in a NORUNIT(X:NORCOLUMNLLOGIC)Q= LAYOUT: BEGIN VAR N-INT; B=BOOLEAN; LINK=LAYOUT; Y=REAL; DO N:= + I FOR B $E X; LINK:= -(1#4) \GB 1#0; GIVE NOR_-UNIT( (N+1)/2 ) \UNION {COLLECT LINK \AT 0*Y FOR Y which takes on the appropriate values so that we place a LINK only at the desired positions } END ENDDEFN The action part of this function does two things.
The slowness of each of these devices is determined by multiplying its pull-up resistance by its capacitance. 9 shows why the voltage on the output node increases at a rate that is inversely proportional to each of the pull-up resistance and the capacitance. That is, if we double the pull-up resistance, charge flows twice as slowly, and if we independently double the capacitance, the output node requires twice as much charge to produce the same voltage. Thus, the slowness of the pull-up process is R*C, where R is the pull-up resistance and C is the capacitance associated with the output node.
19. 19A shows a three-input-NOR gate layout with green links placed not everywhere but only at such positions so that the three NOR gates labeled A, B, and C perform the logical NOR functions shown textually in the figure. 19B shows a symbolic abstraction of the same. 19C shows symbolically an attempt to shrink each NOR gate so that each NOR gate by itself is as small as possible. 19D shows the layout required to implement that shrinking. What do we see? Our optimization of each NOR gate, performed in isolation, yields not an improvement in the overall layout, but a degradation in overall area efficiency.
