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Verification and Scheduling Techniques for Real-Time by Luis Alejandro Cortes

By Luis Alejandro Cortes

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A concept of hierarchy for this design representation is also introduced. Hierarchy is a convenient way to structure the system so that modeling can be done in a comprehensible form. Hierarchi- 32 3. Design Representation cal composition eases the design process when it comes to specifying and understanding large systems. 1 Notions of Equivalence The synthesis process requires a number of refinement steps starting from the initial system model until a more detailed representation is achieved. Such steps correspond to transformations in the system model in such a way that design decisions are included in the representation.

Computationally intensive systems might conveniently be represented by a directed graph where the nodes describe computations and the arcs capture data dependencies between tasks. 1. Modeling 19 atomic operations without side effects. However, the conventional dataflow graph model is inadequate for representing the control unit of systems. Dataflow Process Networks are mainly used for representing signal processing systems [LP95]. Programs are specified by directed graphs where nodes (actors) represent computations and arcs (streams) represent sequences of data.

The verification of Codesign Finite State Machines (CFSMs) has been addressed in [BHJ+ 96]. In this approach, CFSMs are translated into traditional state automata in order to make use of automata theory techniques. The verification task is to check whether all possible sequences of inputs and outputs of the system satisfy the desired properties (specification). The sequences that meet the requirements constitute the language of another automaton. The problem is then reduced to checking language containment between two automata.

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