By Amir M. Rahmani, Pasi Liljeberg, Ahmed Hemani, Axel Jantsch, Hannu Tenhunen
This ebook provides the state-of-the artwork of 1 of the most issues with microprocessors this day, a phenomenon often called "dark silicon". Readers will learn the way strength constraints (both leakage and dynamic energy) restrict the level to which huge parts of a chip should be powered up at a given time, i.e. how a lot genuine functionality and performance the microprocessor provides. The authors describe their examine towards the way forward for microprocessor improvement at the hours of darkness silicon period, overlaying various very important points of darkish silicon-aware architectures together with layout, administration, reliability, and try. Readers will take advantage of particular concepts for mitigating the darkish silicon phenomenon, together with energy-efficient, committed ideas and applied sciences to maximise the usage and reliability of microprocessors.
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Extra resources for The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era
Example text
Adaptive Body Bias (ABB) is not considered here, but is important future work. However, the worst-case variation we used here sets an upper bound on the benefits of ABB. v/min . As for the power, we assume no fine-grained per-core level power management mechanisms; therefore, all cores contribute to the total power consumption through the whole period that the system is in parallel mode. We use the total mean power (p) to estimate the per-core power, so Eq. 7) is rewritten to 28 L. Wang and K. v/ D min.
Bienia, S. Kumar, J. Singh, K. Li, The PARSEC benchmark suite: characterization and architectural implications, in International Conference on Parallel Architectures and Compilation Techniques, PACT ’08 (2008) 2. S. A. Chien, The future of microprocessors. Commun. ACM 54(5) (2011). 1941507 3. A. S. Sohi, A static power model for architects, in International Symposium on Microarchitecture, MICRO ’00 (2000) 4. H. Calhoun, S. Khanna, R. Mann, J. Wang, Sub-threshold circuit design with shrinking CMOS devices, in International Symposium on Circuits and Systems, ISCAS ’09 (2009) 5.
Bienia, S. Kumar, J. Singh, K. Li, The PARSEC benchmark suite: characterization and architectural implications, in International Conference on Parallel Architectures and Compilation Techniques, PACT ’08 (2008) 2. S. A. Chien, The future of microprocessors. Commun. ACM 54(5) (2011). 1941507 3. A. S. Sohi, A static power model for architects, in International Symposium on Microarchitecture, MICRO ’00 (2000) 4. H. Calhoun, S. Khanna, R. Mann, J. Wang, Sub-threshold circuit design with shrinking CMOS devices, in International Symposium on Circuits and Systems, ISCAS ’09 (2009) 5.
