By James B. Kuo
Low-voltage very huge scale integration (VLSI) circuits symbolize the electronics of the long run. All digital items are striving to lessen strength intake to create more cost effective, effective, and compact units. regardless of the inevitable development in the direction of low-voltage, few books handle the expertise wanted. Geared to the desires of engineers and architects within the box, this complete quantity offers a remarkably distinct research of 1 of latest most popular and such a lot compelling examine strategies for VLSI systems.An Instructor's guide proposing particular strategies to the entire difficulties within the publication is out there from the Wiley editorial division.
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Extra info for Low-Voltage CMOS VLSI Circuits
For a PMOS device, its substrate is n-type. By implanting the p-type dopants into the substrate, the doping profile in the substrate direction is counter-doped—a pn junction exists in the surface as shown in Fig. 10(b)—a buried channel. The buried channel structure in the PMOS device is due to the counter-doped channel. In contrast, the NMOS device using the N+ polysilicon gate does not have a buried channel since no pn junction exists in the substrate. Fig. 11 shows the electrostatic potential profile in the substrate direction of a buried-channel PMOS device.
1µm, in addition to the LDD structure described before, two other device structures as shown in Fig. 16 can be used. In the delta-doped MOS device, the delta-doped region is used to avoid channel punchthrough. Above the delta-doped region, the low doping region is used to reduce the short channel effect. In the pocketimplanted MOS device, below the LDD region the pocket-implanted highly doped region has been used to reduce the channel punchthrough. Using the pocket-implanted structure, the drain induced barrier lowering (DIBL) effect can also be suppressed.
After stripping the nitride, a sacrificial oxide of 15nm is grown. After deep-collector photolithography, a high-energy high-dose phosphorus implant is used to form the N+ deep-collector region. Then, two blanket boron implants are used to adjust the threshold voltages of the PMOS and NMOS devices. After stripping the sacrificial oxide, a gate oxide of 15nm is thermally grown. After this step, the LDD structure using the sidewall spacer technique described before is formed. Then a high-dose boron implant is used to form the source/drain region of the PMOS device and the extrinsic base region of the bipolar device.