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Integrated Converters - D to A and A to D Architectures, by Paul G. A. Jespers

By Paul G. A. Jespers

Analog to electronic and electronic to analog converters are crucial interfaces among pcs and the skin international. They interface so much sign processing units and are embedded in an ever higher variety of built-in circuits used for instance within the telecommunications undefined, handheld remote control units, and clinical digital instruments.

This publication surveys fresh growth and provides an account of the operating ideas of built-in converters. It describes the architectures and discusses accuracy and velocity in depth.

The helping site offers MATLAB courses (in UNIX, computing device, and Mac models) which enable the reader to scan with a few of the recommendations defined within the ebook. The appendix describes find out how to use the courses with a purpose to simulate converters on the approach point; 13 examples are given to teach what's possible and the way to run programs.

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This produces a voltage step across Co whose magnitude is equal to Vref multiplied by the ratio of the sum of all capacitances connected to Vref over Co. The output represents thus the analog counterpart of the input coded word. Stray capacitances do not affect this converter. The equivalent network of Fig. 19 shows that neither the capacitance associated with the input nor the output capacitor are of importance. Their charge and discharge currents ignore the summing node. The stray capacitance in parallel with the summing node of the Op Amp is not important either since it belongs to the artificial ground.

This defines the size of the largest and most economic thermometer-coded circuit, while it minimizes the impact of glitches. Generally the optimal converter consists of a low-resolution (two bit) binary-coded converter and a moderate-resolution (eight bit) thermometercoded converter. In the 10-bit converter mentioned above, 256 current sources are arranged in a 16 by 16 RAM-structured array, and deliver each current equal to 4 LSBs while the binary-coded device covers lower contributions. 6 mm2.

First their power consumption is drastically reduced as no DC current flows in the divider. The energy consumption only takes place during the charging and discharging cycles. Second, the DC and AC behaviors can be controlled independently. The output node of a capacitive divider may be precharged so that the output signal will be the attenuated replica of the input plus the pedestal fixed during precharge. This is not possible with resistive dividers. Third, capacitive dividers are strongly sensitive to stray-capacitance.

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