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Continuous-Time Digital Front-Ends for Multistandard by Pieter A. J. Nuyts, Patrick Reynaert, Wim Dehaene

By Pieter A. J. Nuyts, Patrick Reynaert, Wim Dehaene

This booklet describes the layout of totally electronic multistandard transmitter front-ends that may at once force a number of switching strength amplifiers, hence casting off all different analog elements. After reviewing diverse architectures, the authors concentrate on polar architectures utilizing pulse width modulation (PWM), that are totally in line with unclocked hold up traces and different continuous-time electronic undefined. for that reason, readers are enabled to shift accuracy matters from the voltage area to the time area, to coincide with submicron CMOS know-how scaling. The authors current various architectural ideas and evaluate them, according to their influence at the sign and spectrum caliber. subsequent, a high-level theoretical research of 2 diversified PWM-based architectures – baseband PWM and RF PWM – is made. at the circuit point, conventional electronic elements and layout innovations are revisited from the viewpoint of continuous-time electronic circuits. vital layout standards are pointed out and diversified recommendations are provided, besides their benefits and downsides. eventually, chips designed in nanometer CMOS applied sciences are defined, besides size effects for validation.

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This expression has three parameters: the amplitude a , the frequency f c (the index c is commonly used to indicate that f c is the carrier frequency) and the phase ω. Each of these parameters can be varied to modulate information onto the wave, which then becomes a carrier. 1 Amplitude Modulation Amplitude modulation (AM) consists of varying the amplitude of a carrier to modulate information onto it. Thus, the amplitude now becomes a function of time, called the AM signal a(t). 2) where ω is an arbitrary constant and is usually normalized to 0.

26 2 Digital Transmitter Architectures: Overview Fig. 6 Class-E amplifier Vdd Ld Vin C Cd L RL It can be shown that the amplitude of the sinusoidal current is equal to 2Vdd /(π R L ), which in the figure was normalized to 2/π . In practice, CMOS transistors exhibit significant parasitic capacitances and resistances. Apart from putting an upper bound on the operating frequency (regardless of the LC filter), these also reduce the efficiency: The resistance dissipates some of the power that flows through the transistors, and the capacitance of the nMOS is charged to the supply voltage Vdd when the pMOS transistor is conducting.

Furthermore, the multiplier only needs to be able to multiply with 1 and −1. Finally, since every second sample will be multiplied by 0, these samples need not be produced, so that the multipliers and preceding circuits can operate at 2 f c rather than 4 f c [15]. The input signals i(t) and q(t) can be encoded into two-level signals with levels ±1 using several coding schemes such as baseband pulse width modulation (PWM) [37] (Sect. 3) or baseband modulation [15, 16, 69] (Sect. 1). In this case, the multiplier only needs to be able to either replicate its input signal or invert it.

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