By Mikko E. Waltari
For 4 many years the evolution of built-in circuits has Moore’s legislation, based on which the variety of transistors in keeping with sq. millimeter of silicon doubles each 18 months. while transistors became quicker, making attainable ever-increasing clock charges in electronic circuits. This pattern turns out set to proceed for a minimum of one other decade with no slowing down. therefore, within the close to destiny the processing energy of electronic circuits will proceed to extend at an accelerating speed. For analog circuits the evolution of expertise isn't really as important. therefore, there's a pattern to maneuver sign processing features from the analog area to the electronic one, which, in addition to bearing in mind the next point of accuracy, offers reductions in strength intake and silicon sector, raises robustness, accelerates the layout approach, brings flexibility and programmability, and raises the chances for layout reuse. in lots of functions the enter and output signs of the approach are inherently analog, combating all-digital realizations; not less than a conversion among analog and electronic is required on the - terfaces. regularly, relocating the analog-digital boundary toward the skin international raises the bit cost throughout it. In telecommunications structures the fashion to spice up bit premiums relies on - ploying widerbandwidths and a better signal-to-noise ratio. whilst radio architectures in lots of functions are evolving towards software-defined radio, one of many major features of that's the transferring of the anal- electronic boundary towards the antenna.
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Additional info for Circuit Techniques for Low-Voltage and High-Speed A/D Converters
Sample text
In hold mode the signal at the output of the input buffer couples to the hold capacitor through the parasitic base-emitter capacitor of Q5. The feedthrough is minimized by connecting a feed-forward capacitor C1 from the other output of S/H Circuit Architectures 59 the input buffer to the hold node. This capacitor is implemented by employing the base-emitter junction capacitance of a BJT. 2 GS/s in [105], mainly through the use of a more advanced technology. However, the increased speed was paid for by decreased linearity (from 10 bits to 8 bits) and increased power consumption (from 40 mW to 460 mW).
5-bit stage. 13. The signal range both in the input and in the output is from Nominally, the comparator decision levels are set to and the ADC output codes for the three regions are “00”, “01” and “10”. A/D Converters 45 Comparator offset can shift the decision level, as shown in the figure with the dashed line. Consequently, the ADC output code remains “00” instead of “01”. The residue, however, stays in the input range of the next stage, which is all that matters, as discussed earlier. The final conversion result is the sum of all the subtracted reference voltages.
The minimum size of the sampling capacitor is limited by the droop rate of the held output. To make the droop smaller, the bias current of the first emitter follower (Q8) in the output buffer is turned off in hold mode. The droop in the differential output signal is considerably smaller than in the case of single output, since it is mostly common mode. In hold mode the signal at the output of the input buffer couples to the hold capacitor through the parasitic base-emitter capacitor of Q5. The feedthrough is minimized by connecting a feed-forward capacitor C1 from the other output of S/H Circuit Architectures 59 the input buffer to the hold node.
